📚 node [[tpu_chip|tpu chip]]
Welcome! Nobody has contributed anything to 'tpu_chip|tpu chip' yet. You can:
-
Write something in the document below!
- There is at least one public document in every node in the Agora. Whatever you write in it will be integrated and made available for the next visitor to read and edit.
- Write to the Agora from social media.
-
Sign up as a full Agora user.
- As a full user you will be able to contribute your personal notes and resources directly to this knowledge commons. Some setup required :)
⥅ related node [[tpu_chip]]
⥅ node [[tpu_chip]] pulled by Agora
📓
garden/KGBicheno/Artificial Intelligence/Introduction to AI/Week 3 - Introduction/Definitions/Tpu_Chip.md by @KGBicheno
TPU chip
Go back to the [[AI Glossary]]
A programmable linear algebra accelerator with on-chip high bandwidth memory that is optimized for machine learning workloads. Multiple TPU chips are deployed on a TPU device.
📖 stoas
- public document at doc.anagora.org/tpu_chip|tpu-chip
- video call at meet.jit.si/tpu_chip|tpu-chip
🔎 full text search for 'tpu_chip|tpu chip'